Dynamic Random Access Memory (DRAM) is a type of memory that stores each bit of data in a separate capacitor within an integrated circuit (IC). The capacitor may be charged or discharged to represent two values of a bit. Since capacitors will slowly leak over time, the charge on the capacitor must be refreshed periodically to maintain the value of the bit hence the use of the term “dynamic.” The primary memory in personal computing devices is often DRAM.
DRAM is manufactured as Integrated Circuits (ICs) bonded and mounted into packages with contacts for electrical connection to control signals and buses. In early use, DRAM ICs were installed directly to the motherboard; later, DRAM ICs were assembled into multi-chip plug-in modules, e.g., Single In-line Memory Modules (SIMMs) and Dual In-line Memory Modules (DIMMs). Both SIMMs and DIMMs comprise a series of DRAM ICs mounted on one or both sides of a printed circuit board. In contrast to SIMMs that include redundant contacts on both sides, DIMMs include distinct contacts on each side of the printed circuit board.
DIMMs may be constructed to specific standards, e.g., Rambus Dynamic Random Access Memory (RDRAM), Double Data Rate Type Two or Second Generation (DDR2), and Double Data Rate Type Three or Third Generation (DDR3), and to specific hardware systems, e.g., notebook computers, personal computers, and servers. A DIMM built for DDR2 notebook computers would be constructed according to a DDR2 200-pin SO-DIMM memory module standard, while a DIMM intended for a DDR3 server system would be built according to a DDR3 240-pin registered-DIMM standard.
In some cases, the load presented by a DIMM may adversely affect signal integrity. Load reduction is required in at least some DIMMs because each additional DIMM added into a system may degrade the integrity of the signal transmitted to other DIMMs in that memory channel, which creates a tradeoff between total system memory capacity and total system performance. By utilizing DIMMs with load reduction buffers, the electrical loading and associated degradation contributed by each DIMM is minimized, thereby enabling the installation of several DIMMs per memory channel without significant degradation in performance.